1. Field of the Invention
This invention relates generally to a circuit and method for using a stable asynchronous clock source to perform glitch-free regeneration of a clock for a synchronous interface that is not free from glitches.
2. Description of Related Art
The fields of application specific integrated circuits (ASIC) using field programmable gate arrays (FPGA), the design of such circuits, synchronous interfaces between circuit boards, telecommunications, and digital subscriber line access multiplexers (DSLAM), including redundant DSLAMs, are known. Likewise, the use of network termination (NT) cards and Utopia level two (L2) interfaces between two redundant NT cards is similarly known.
One known use for standard Utopia L2 interfaces between two redundant NT cards is to pass asynchronous transfer mode (ATM) traffic between two redundant NT cards. Such systems establish a synchronous interface between the two redundant NT cards. An example of such a system is an NT card redundant internet protocol (IP)/ATM DSLAM. Using the example of the foregoing systems, it is desirable to incorporate a glitch free clock regenerator.
Any of the foregoing objects and advantages are illustrative of those that can be achieved by various exemplary embodiments. They are not intended to be interpreted as required of all possible embodiments, and they are not intended to be exhaustive or limiting of the possible advantages which can be realized. Thus, these and other objects and advantages of various exemplary embodiments will be apparent from the description herein or can be learned from practicing various exemplary embodiments, both as embodied herein or as modified in view of any variation which may be apparent to those skilled in the art. Accordingly, the present invention resides in the novel methods, arrangements, combinations and improvements herein shown and described in various exemplary embodiments.